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EL5325A
Data Sheet May 8, 2006 FN7447.1
12-Channel TFT-LCD Reference Voltage Generator with External Shutdown
The EL5325A with external shutdown is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the 3-wire, SPI compatible interface. A number of EL5325A can be stacked for applications requiring more than 12 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. The EL5325A has 12 outputs and is available in a 28 Ld TSSOP package. They are specified for operation over the full -40C to +85C temperature range.
Features
* 12-channel reference outputs * Accuracy of 1% * Supply voltage of 5V to 16.5V * Digital supply 3.3V to 5V * Low supply current of 10mA * Rail-to-rail capability * Internal thermal protection * External shutdown * Pb-free plus anneal available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Reference voltage generators
Ordering Information
PART NUMBER EL5325AIREZ (Note) EL5325AIREZ-T7 (Note) PART TAPE & MARKING REEL 5325AIREZ 5325AIREZ 7" 13" 7" 13" PACKAGE PKG. DWG. #
Pinout
EL5325A (28 LD TSSOP/HTSSOP) TOP VIEW
ENA 1 SDI 2 SCLK 3 SDO 4 EXT_OSC 5 VS 6 28 OUTA 27 OUTB 26 OUTC 25 GND 24 OUTD 23 OUTE 22 OUTF 21 OUTG 20 OUTH 19 OUTI 18 GND 17 OUTJ 16 OUTK 15 OUTL
28 Ld HTSSOP MDP0048 (Pb-Free) 28 Ld HTSSOP MDP0048 (Pb-Free) 28 Ld HTSSOP MDP0048 (Pb-Free) 28 Ld TSSOP (Pb-Free) 28 Ld TSSOP (Pb-Free) 28 Ld TSSOP (Pb-Free) MDP0044 MDP0044 MDP0044
EL5325AIREZ-T13 5325AIREZ (Note) EL5325AIRZ (Note) EL5325AIRZ-T7 (Note) EL5325AIRZ-T13 (Note) 5325AIRZ 5325AIRZ 5325AIRZ
SHDN 7 VSD 8 REFH 9 REFL 10 VS 11 GND 12 CAP 13 NC 14
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5325A
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS & GND . . . . . . 4.5V (min) to 18V (max) Supply Voltage between VSD & GND . 3V (min) to VS and 7V (max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS ISD ANALOG VOL VOH ISC PSRR tD VAC VMIS VDROOP RINH REG CAP DIGITAL VIH Supply Current
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
No load
10.2 0.17
12.5 0.35
mA mA
Digital Supply Current
Output Swing Low Output Swing High Short Circuit Current Power Supply Rejection Ratio Program to Out Delay Accuracy referred to the ideal value Channel to Channel Mismatch Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation Band Gap
Sinking 5mA (VREFH = 15V, VREFL = 0) Sourcing 5mA (VREFH = 15V, VREFL = 0) RL = 10 VS+ is moved from 14V to 16V 14.85 100 45
50 14.95 140 65 4
150
mV V mA dB ms mV mV
Code = 512 Code = 512
20 2 1 32 2
mV/ms k
IOUT = 5mA step By pass with 0.1F 1
0.5 1.3
1.5 1.6
mV/mA V
Logic 1 Input Voltage
VSD = 5V VSD = 3.3V
4 2 5
V V MHz V ns ns ns ns ns G s % LSB LSB kHz V 100 A
FCLK VIL tS tH tLC tCE tDCO RSDIN TPULSE Duty Cycle INL DNL F_OSC VIH_SHDN IIH_SHDN
Clock Frequency Logic 0 Input Voltage Setup Time Hold Time Load to Clock Time Clock to Load Line Clock to Out Delay Time SDIN Input Resistance Minimum Pulse Width for EXT_OSC Signal Duty Cycle for EXT_OSC Signal Integral Nonlinearity Error Differential Nonlinearity Error Internal Refresh Oscillator Frequency SHDN Voltage Input High SHDN Current Input High SHDN = 2V OSC_Select = 0 2 Negative edge of SCLK VSD = 3.3V/5V 20 20 20 20 10 1 5 50 1.3 0.5 21
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2
EL5325A Pin Descriptions
EL5325A 1 2 3 4 5 6, 11 7 8 9 10 12 13 14 17 19 20 21 22 23 24 26 27 28 15 16 18, 25 PIN NAME ENA SDI SCLK SDO EXT_OSC VS+ SHDN VSD REFH REFL GND CAP NC OUTJ OUTI OUTH OUTG OUTF OUTE OUTD OUTC OUTB OUTA OUTL OUTK GND Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Power PIN TYPE Logic Input Logic Input Logic Input Logic Output Logic Input/Output Analog Power Logic Input Digital Power Analog Reference Input Analog Reference Input Ground Analog Bypass Pin PIN FUNCTION Chip select, low enables data input to logic Serial data input Serial data clock Serial data output External oscillator input or internal oscillator output Positive supply voltage for analog circuits Chip shutdown: float enables chip, high > 2V disables chip Positive power supply for digital circuits (3.3V - 5V) High reference voltage Low reference voltage Ground Decoupling capacitor for internal reference generator, 0.1F Not connected Channel J programmable output voltage Channel I programmable output voltage Channel H programmable output voltage Channel G programmable output voltage Channel F programmable output voltage Channel E programmable output voltage Channel D programmable output voltage Channel C programmable output voltage Channel B programmable output voltage Channel A programmable output voltage Channel L programmable output voltage Channel K programmable output voltage Ground
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EL5325A Typical Performance Curves
DIFFERENTIAL NONLINEARITY (LSB) VS=15V, VSD=5V, VREFH=13V, VREFL=2V 0.3 0.2 0.1 INL (LSB) 0.5 0 -0.5 -1 210 410 610 810 1010 0 200 400 600 CODE 800 1000 1200 INPUT CODE 0 -0.1 -0.2 -0.3 10 1.5 1 REFH=13V, REFL=2V
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
VS=VREFH=15V M=400ns/DIV 0mA 5mA CL=4.7nF RS=20 5V CL=1nF RS=20 CL=180pF 200mV/DIV 5mA/DIV 5mA 0mA
VS=VREFH=15V M=400ns/DIV
CL=1nF RS=20
CL=4.7nF RS=20 CL=180pF
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
M=400s/DIV
M=400s/DIV
5V 0V
SCLK
SCLK
SDA 5V 0V 10V 5V 0V OUTPUT
SDA
OUTPUT
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V)
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EL5325A Typical Performance Curves (Continued)
M=400s/DIV SCLK 5V 0V 5V 0V OUTPUT 200mV OUTPUT SDA M=400s/DIV
SCLK
SDA
0V
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V TO 200mV)
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 0V)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 POWER DISSIPATION (W) POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C)
JA =
833mW
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 1.333W
JA =
TS S
12
O P2 0 8 C/ W
SO P2 75 8 C /W
TS
FIGURE 9. POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 10. POWER DISSIPATION vs AMBIENT TEMPERATURE
1 POWER DISSIPATION (W) 0.9
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W)
3.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
0.8 909mW
H 8 P2 /W SO C TS 110 =
3 3.333W 2.5 2 1.5 1 0.5 0 0 25
8 P2 W O / S S 0 C HT =3 A J
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25
AMBIENT TEMPERATURE (C)
FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE
J
A
50
75 85 100
125
150
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 12. POWER DISSIPATION vs AMBIENT TEMPERATURE
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EL5325A General Description
The EL5325A provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5325A, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5325A. As all of the output buffers are identical, it is also possible to use the EL5325A for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy. allocated to the following functions (also refer to the Control Bits Logic Table) * Bit 15 is always set to a zero * Bit 14 controls the source of the clock, see the next section for details * Bits 13 through 10 select the channel to be written to, these are binary coded with channel A = 0, and channel H=7 * The 10-bit data is on bits 9 through 0. Some examples of data words are shown in the table of Serial Programming Examples
TABLE 1. CONTROL BITS LOGIC TABLE BIT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 NAME Test Oscillator A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Always 0 0 = Internal, 1 = External Channel Address Channel Address Channel Address Channel Address Data Data Data Data Data Data Data Data Data Data
Digital Interface
The EL5325A uses a simple 3-wire SPI compliant digital interface to program the outputs. The EL5325A can support the clock rate up to 5MHz.
Serial Interface
The EL5325A is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. To facilitate the system designs that use multiple EL5325A chips, a buffered serial output of the shift register (SDO pin) is available. Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. To control the multiple EL5325A chips from a single threewire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next chip. While the ENA is held low, the 16m-bit data is loaded to the SDI input of the first chip. The first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. While the ENA is held high, all addressed outputs will be updated simultaneously. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are
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EL5325A Serial Timing Diagram
ENA
tHE
tSE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B15 MSB
B14
B13
B12-B2
B1
B0 LSB t
Load MSB first, LSB last
TABLE 2. SERIAL TIMING PARAMETERS PARAMETER T tr/tf tHE tSE tHD tSD tW RECOMMENDED OPERATING RANGE 200ns 0.05 * T 10ns 10ns 10ns 10ns 0.50 * T Clock Period Clock Rise/Fall Time ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width DESCRIPTION
TABLE 3. SERIAL PROGRAMMING EXAMPLES CONTROL C1 0 0 0 0 0 0 C0 0 0 0 0 0 1 CHANNEL ADDRESS A3 0 0 0 0 0 0 A2 0 0 0 0 1 1 A1 0 0 0 1 1 1 A0 0 0 0 1 1 1 D9 0 1 1 1 0 0 D8 0 1 0 0 0 0 D7 0 1 0 0 0 0 D6 0 1 0 0 0 0 DATA CONDITION D5 0 1 0 0 0 0 D4 0 1 0 0 1 1 D3 0 1 0 0 1 1 D2 0 1 0 0 1 1 D1 0 1 0 0 1 1 D0 0 1 0 1`t 1 1 Internal Oscillator, Channel A, Value = 0 Internal Oscillator, Channel A, Value = 1023 Internal Oscillator, Channel A, Value = 512 Internal Oscillator, Channel C, Value = 513 Internal Oscillator, Channel H, Value = 31 External Oscillator, Channel H, Value = 31
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EL5325A Block Diagram
REFERENCE HIGH
OUTA
OUTB
OUTJ EIGHT CHANNEL MEMORY VOLTAGE SOURCES OUTK
OUTL
REFERENCE LOW REFERENCE DECOUPLE CLK SDI LOAD SDO
CONTROL IF
FILTER
EXT_OSC
Analog Section
TRANSFER FUNCTION The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 1024
CLOCK OSCILLATOR The EL5325A requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting B14 to high, the
where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5325A will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5325A. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 12 channels, the system can be designed such that one EL5325A will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5325A can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way.
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EL5325A
chip is on external clock mode. Setting B14 to low, the chip is on internal clock mode. CHANNEL OUTPUTS Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. In the worst-case scenario this will be 576s when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 4.6ms to 5.2ms depending on the absolute timing relative to the update cycle. POWER DISSIPATION AND THERMAL SHUTDOWN With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
when sinking. Where: * i = 1 to total 12 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The EL5325A has an internal thermal shutdown circuitry that prevents overheating of the part. When the junction temperature goes up to about 150C, the part will be disabled. When the junction temperature drops down to about 120C, the part will be enabled. With this feature, any short circuit at the outputs will enable the thermal shutdown circuitry to disable the part. POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5325A. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5325A should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. APPLICATION USING THE EL5325A In the first application drawing, the schematic shows the interconnect of a pair of EL5325A chips connected to give 12 gamma corrected voltages above the VCOM voltage, and 12 gamma corrected voltages below the VCOM voltage.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
External Shutdown
The EL5325A also has an external shutdown to enable and disable the part. The SHDN pin should never be driven low. Rather, to enable the part, the SHDN pin must be left open (float). To disable, the SHDN pin must be driven HI (>2V). WIth this feature, the EL5325A can be forced to shut down, regardless of any other conditions. A simple open collector driver is adequate to control the enable and disable function:
VSD R1 100K R2 100K SHDN Q1 PNP
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
EL5325A SHDN
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EL5325A Application Drawing
HIGH REFERENCE VOLTAGE +10V 0.1F +12V 0.1F MICROCONTROLLER +5V 0.1F OUTD SDI SCK ENA SDO OSC OUTF CAP 0.1F OUTK REFL GND OUTL VSD OUTC VS OUTB REFH OUTA
COLUMN (SOURCE) DRIVER
LCD PANEL
OUTE
LCD TIMING CONTROLLER
HORIZONTAL RATE
EL5325A +5.5V MIDDLE REFERENCE
REFH OSC +12V 0.1F +5V 0.1F VSD VS
OUTA
OUTB
OUTC
OUTD SDI SCK ENA CAP 0.1F LOW REFERENCE VOLTAGE +1V 0.1F REFL OUTK OUTE
OUTF
GND
OUTL
EL5325A
10
EL5325A Package Outline Drawing (HTSSOP)
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EL5325A TSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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